有没得大佬帮看看代码?抢答器的蜂鸣器要求有抢到信号进来后响应三秒后停止,但这个代码上班后,蜂鸣器一直响不会自动停。
module beep(clk, beep, L5, L6, L7, L8);input clk, L5, L6, L7, L8;output beep;reg beep_r = 1;reg [lbk]27:0[rbk] count;wire [lbk]27:0[rbk] three_seconds = 3_000_000_000; // 3秒钟的时钟周期数
assign beep = beep_r;
always @(posedge clk) begin if (L5 | L6 | L7 | L8) begin if (count < three_seconds) begin beep_r <= ~beep_r; count <= count + 1; end else begin count <= 0; beep_r <= 0; // 三秒后停止发声 end end else begin count <= 0; beep_r <= 0; // 如果没有输入信号,则停止发声 endendendmodule#Verilog#抢答器##EDA课设##蜂鸣器##FPGA#
module beep(clk, beep, L5, L6, L7, L8);input clk, L5, L6, L7, L8;output beep;reg beep_r = 1;reg [lbk]27:0[rbk] count;wire [lbk]27:0[rbk] three_seconds = 3_000_000_000; // 3秒钟的时钟周期数
assign beep = beep_r;
always @(posedge clk) begin if (L5 | L6 | L7 | L8) begin if (count < three_seconds) begin beep_r <= ~beep_r; count <= count + 1; end else begin count <= 0; beep_r <= 0; // 三秒后停止发声 end end else begin count <= 0; beep_r <= 0; // 如果没有输入信号,则停止发声 endendendmodule#Verilog#抢答器##EDA课设##蜂鸣器##FPGA#